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DE248 Drive Electronics

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(Last Modified: 04 November 2010 06:08:40 PM )

System-level Documentation

• Overview

• Hardware Platform

• Instruction Manual

• HOST/FPGA Register Map (blank)

• UCF File Description

• Xilinx Webpack Configuration

Firmware Modules

• HOST/FPGA Register Space

• General Purpose User I/O

• RS-232 to Register Module

  • ASCII to Binary Module

  • Binary to ASCII Module

  • RS-232 Packet Module

    • Packet Buffer Module

    • Packet Receiver Controller Module

    • Packet Transmitter Controller Module

    • RS-232 w/Echo Module

      • Echo Controller

      • RS-232 w/FIFO Module

        • RS-232 Receiver Controller Module

        • RS-232 Transmitter Controller Module

        • RS-232 Xon/Xoff Controller Module

        • RS-232 Physical Layer Module

          • RS-232 PHY Oscillator Module

          • RS-232 PHY Receiver Module

          • RS-232 PHY Transmitter Module

• SPI Master Module

• Programmable Clock Generator Module

• Memory Interface Module (blank)

• Loop Controller Module (blank)

• DIO2 Interface Module

• Test Tap Module (blank)

• Gray Code Module (blank)

• Support Modules (blank)

  • Registers

  • Pulse Generators (8, 16, 24)-bit

• BFE ASIC-equivalent Modules

  • Programmable Signal Generator Module

  • Window Counter Module

General Information

• RS232 Serial Communications

• Gray Codes

• SPI - Serial Peripheral Interface (blank)

• Binary to BCD conversion

• Binary Division

Source Code Files

Note: The actual file names have been appended with a ".txt" extension so that they will display in the browser appropriately.

Last updated: 15 March 2008

• de248.ucf

• de248.v

• ascii.v

• bfe.v

• loopcontroller.v

• mem1.v

• regspace.v

• rs232.v

• rs232tomem.v

• spi.v

• support.v