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GENERAL PURPOSE USER I/O MODULE
(Last Modified: 04 November 2010 06:08:32 PM )
There are two types of General Purpose User I/O on the DE248. The first permits the arbitrary assignment of input or output of thirty-two pins and allows the user to read from or write to up to eight of these pins with a single command. The other type is a bank of fourteen output only pins configured so that user may set or clear each output with a command that is independent of the state of the other pins.
There is no actual Verilog module for this block. This code is implemented as a direct mapping between the HOST/FPGA Register Space and the Port Pins.
There are presently 32 pins on Port C that are connected to bidirectional I/O buffers. The direction control lines of those buffers are controlled by four of the HOST registers. Another four HOST registers are used to write data to those buffers and four FPGA buffers are used to read the output of those buffers.
The OE register is a bitmask wherein any bit that is '1' configures that port for output. Writing to ports configured as input has no effect. Reading from ports configured as outputs will return the actual value on the port pin.
The port to signal mapping is intended to place nearby pins in different nibbles of different registers, however it also reflects a need to map around pins that were already in use for the SPI interface.
The BFE297 test board has the following GPIO signals:
To configure the five output signals for output, perform the following:
#> W2812 ! Configure C13, C21 for output
#> W2912 ! Configure C15, C23 for output
#> W2A02 ! Configure C25 for output
At this point, the following are the relevant register writes for controlling the outputs:
#> W2000 ! Vtest2=LO \Prst=LO
#> W2002 ! Vtest2=LO \Prst=HI
#> W2010 ! Vtest2=HI \Prst=LO
#> W2012 ! Vtest2=HI \Prst=HI
#> W2100 ! Vtest1=LO Ptg=LO
#> W2102 ! Vtest1=LO Ptg=HI
#> W2110 ! Vtest1=HI Ptg=LO
#> W2112 ! Vtest1=HI Ptg=HI
#> W2200 ! Pclk=LO
#> W2202 ! Pclk=HI
To read the Tdo signal, perform the following register read:
#> RA2 ! Tdo is HI iff upper nibble is odd
While the banked I/O signals make it possible to read from or write to many signals with comparably few commands, it also tends to make it difficult to determine which commands should be sent to change a particular signal without affecting other signals. For this reason, a bank of signals that permit the User to set and clear individual signals with commands that are independent of the state of other signals has been implemented.
This module has fourteen signals and is controlled by a single HOST register (presently 0x17). The lower nibble is used to select outputs that are to be set and the upper nibble is used to select outputs that are to be cleared. If a nibble is set to zero, then no action is taken on any of the outputs while if a nibble is set to all ones then action is taken on all of the signals. For instance, the following commands perform the actions indicated in the comments.
#> W1700 ! Take no action of any kind.
#> W1706 ! Set output #6
#> W170D ! Set output #D (13)
#> W1760 ! Clr output #6
#> W17D3 ! Clr output #D (13) and set output #3
#> W170F ! Set all 14 outputs
#> W17F0 ! Clr all 14 outputs
#> W17FF ! Will clear all outputs
#> W174F ! Will set all outputs except #4
If the command tells the module to both set and clear a given bit, the clear will take precedence in a static sense. Since the changes are registered, the bits that are told to set should not glitch, but it is still recommended not to issue contradictory commands.