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DE248 Drive Electronics


(Last Modified: 04 November 2010 06:08:58 PM )

Top Level Instantiation

// ======================================================================
// Signal Generator Bank
// ======================================================================

wire [ 7:0] SG_D, SG_A, SG_C;
wire [15:0] SG_X;
wire [ 7:0] SG_Q;
wire [ 7:0] SG_Test;

wire SG_WS;
assign SQ_WS = SG_C[0];

    .Q(SG_Q), .X(SG_X), // Signal outputs and counter input
    .D(SG_D), .A(SG_A), .WS(SG_WS), // Register Interface
    .ID_CR(6'b010001), .ID_ER(3'b011), // Control and Edge Register IDs
    .StaticDefaults (8'b00000000),
    .SourceDefaults (8'b00000000),
    .ExtDefaults (8'b00000000),
    .Rise0(8'd1), .Fall0(8'd2),
    .Rise1(8'd3), .Fall1(8'd8),
    .Rise2(8'd9), .Fall2(8'd11),
    .Rise3(8'd10), .Fall3(8'd43),
    .Rise4(8'd42), .Fall4(8'd43),
    .Rise5(8'd0), .Fall5(8'd0),
    .Rise6(8'd9), .Fall6(8'd10),
    .Rise7(8'd10), .Fall7(8'd42),
    .ForceRiseB(8'hFF), .ForceFallB(8'hFF), // Force Rise and Fall inputs
    .PrstB(~rst), .Pclk(clk) // Global Signals

wire Mclk, MclkTick, MclkRise, MclkFall;
wire [7:0] MclkDiv;
PulseGen8 MCLKGEN (.Q(MclkTick), .Period(MclkDiv), .en(HI), .rst(rst), .clk(clk));
DFFRen MCLK (.Q(Mclk), .D(~Mclk), .en(MclkTick), .rst(rst), .clk(clk));
assign MclkRise = ((MclkTick == HI)&&(Mclk == LO));
assign MclkFall = ((MclkTick == HI)&&(Mclk == HI));

wire WC_TC;
WindowCounter16 MCNT (
.Q(SG_X), .TC(WC_TC), .CE1(MclkRise), .CE2(HI), .LoadB(~WC_TC),
.D(SG_D), .A(SG_A), .ID(6'b000000), .WS(SG_WS), .Start(16'd0), .Stop(16'd50),
.PrstB(~rst), .Pclk(clk)


User-level Description

This module is a near-direct implementation of the Programmable Signal Generator Bank on the BFE297. It consists of eight programmable pulse generators synced to a common 16-bit counter (the BFE297 uses a 12-bit counter). In normal operation, each signal output is asserted and deasserted at times (counter output values) that are programmed into the Edge Control Register. The Edge Control Register is configured with default times that are loaded during any global reset and that may be overwritten via the HOST interface.


 consists of a set of eight pulse generators and a related set of eight square wave generators. Each pulse generator produces a single HI pulse one every X clock cycles where X is a user-programmable parameter. The maximum period of X is dependent on which of the eight channels is used - there are two 8-bit channels, four 16-bit channels, and two 24-bit channels. In addition to the pulse outputs, each channel is capable of producing a square wave output in which the square wave toggles state coincident with each output pulse.

is actually a family of modules. One subfamily are pulse generators and the other subfamily are square wave generators. The pulse generators output a HI pulse once every period of X clock cycles where X is a programmable parameter.

Module Code


Theory of Operation