/*=================================================================*/
/*===  ASCII Related Modules ======================================*/
/*=================================================================*/

/* 
 * FILE: ascii.v
 * PROGRAMMER: William L. Bahn
 *
 * CONTENTS:
 *
 * OVERVIEW
 * 
 * This file contains parameter definitions and modules related to
 * processing ASCII characters.
 */

//=================================================================
// ASCII to BINARY Converter
//=================================================================
/*
 * MODULE: Ascii2Binary()
 *
 * This module builds and holds the binary value represented by a 
 * pair of ASCII codes representing hexadecimal digits. There is a
 * single input for the ASCII code and two write enable lines to 
 * control whether the converted value is written to the upper or 
 * lower nibble of the output register.
 *
 * The output is registered at the rising edge of the master clock
 * when the write enable signal is asserted.
 *
 * It assumed that the two ASCII characters represent valid hexadecimal
 * characters. If they do not, a conversion will still take place but
 * the result is undefined.
 */

module Ascii2Binary(binary, ascii, WE_MSB, WE_LSB, rst, clk);

	parameter LO = 1'b0, HI = 1'b1;

	output [7:0] binary;
	input  [7:0] ascii;
	input WE_MSB, WE_LSB;
	input rst, clk;

	wire [3:0] nibble;

	Ascii2Nibble A2N
	(
		.nibble(nibble), .ascii(ascii)
	);

	Reg4 MSN
	(
		.Q(binary[7:4]), .D(nibble), .en(WE_MSB), .rst(rst), .clk(clk)
	);

	Reg4 LSN
	(
		.Q(binary[3:0]), .D(nibble), .en(WE_LSB), .rst(rst), .clk(clk)
	);

endmodule

//=================================================================
// BINARY to ASCII Converter
//=================================================================
/*
 * MODULE: Binary2Ascii()
 *
 * This module builds generates the two ASCII codes that form the 
 * hexadecimal representation for the eight-bit value presented at
 * its input. The conversion results are latched on the rising edge
 * of the master clock when the write enable line is asserted.
 * 
 * When the HiByte input is HI, the character representing the most 
 * significant nibble is output, otherwise the character representing
 * the least significant character is output.
 */

module Binary2Ascii(ascii, binary, WE, rst, clk);

	parameter LO = 1'b0, HI = 1'b1;

	output [15:0] ascii;
	input  [7:0] binary;
	input  WE;
	input  rst, clk;

	wire [15:0] ascii_temp;

	Nibble2Ascii MSB 
	(
		.ascii(ascii_temp[15:8]), .nibble(binary[7:4])
	);

	Reg8 REG_MSB
	(
	 	.Q(ascii[15:8]), .D(ascii_temp[15:8]), .en(WE), .rst(rst), .clk(clk)
	);

	Nibble2Ascii LSB 
	(
		.ascii(ascii_temp[7:0]), .nibble(binary[3:0])
	);

	Reg8 REG_LSB 
	(
		.Q(ascii[7:0]), .D(ascii_temp[7:0]), .en(WE), .rst(rst), .clk(clk)
	);

endmodule

module Nibble2Ascii(ascii, nibble);

	parameter LO = 1'b0, HI = 1'b1;

	output [7:0] ascii;
	input  [3:0] nibble;

	wire IsDecimal;

	assign IsDecimal = ((nibble < 4'd10)? HI : LO);

	assign ascii[7:4] = ((IsDecimal == HI)? 4'b0011:4'b0100);
	assign ascii[3:0] = nibble - ((IsDecimal == HI)? 4'd0:4'd9);

endmodule

//=================================================================
// ASCII to NIBBLE Converter
//=================================================================
/*
 * MODULE: Ascii2Nibble()
 * 
 * This is a combinatorial module that converts an 8-bit ASCII code
 * to the 4-bit binary nibble the character represents according to
 * a hexadecimal interpretation.
 */

module Ascii2Nibble(nibble, ascii);

	parameter LO = 1'b0, HI = 1'b1;

	output [3:0] nibble;
	input  [7:0] ascii;

	wire IsDecimal;

	assign IsDecimal = ((ascii[7:4] == 4'b0011)? HI : LO);

	assign nibble = ascii[3:0] + ((IsDecimal == HI)? 4'd0:4'd9);
	
endmodule