The ECE-3220 Panic Page
(Last Modified: 04 November 2010 06:11:57 PM )
The Panic Page is a place to come to see if the cause of your frustrations have already been hashed through by someone else. This should become the first place you come for assistance as I hope to post the results of conversations and e-mails with students here if I feel that others may benefit. Rest assured, any such post will be completely sanitized of any identifying information.
04 MAY 03 - Update on what to expect on Exam #3
While I touched on this last week and we will go over this in detail on Tuesday in class, I wanted to give everyone an additional head's up on what to expect on the Exam on Thursday.
The homework solutions in the library will only be for HW#9 and HW#10 and part of HW#11. I have simply been too swamped with stuff at work and in assisting students on DP#3 to get the rest of the solutions worked out and posted. As a result, I'm sure that some of you are going to be stressed about being tested on material for which no worked examples were available (even though most indications are that the majority of the class has never looked at the binder in the library in the first place). So I wanted to reassure you that this should not have a significant adverse effect. As you should be very aware by now, I stress comprehension of the fundamental concepts. For the material in this chapter, that really comes down to Sec 7.2. The bulk of the rest of the chapter is simply putting those principles into practice and making a few comments on the results such as the bandwidth limiting nature of the Miller Effect and how the cascode configuration gets around that.
So, for the exam, you want to be able to discuss the underlying principles of this chapter and how those principles are put into practice. If you understand and can describe the development outlined below, you should do fine on the exam. The circuits on the exam will be focussed on applying the principles described below in order to modify the original circuit into one that is suitable for finding the DC bias point, the midband gain, the lower cutoff-frequency, or the upper cutoff frequency. This will constitute the vast majority of the points on the exam.
The remainder of the points will come for being able to derive and use Miller's Theorem, being able to discuss the implications of the Miller Effect on a Common Collector amplifier and how the Common Base amplifier avoids this effect, and being able to actually determine the resistance seen by a capacitor. This last will be the only significant circuit analysis task on the exam (you can expect to see a DC Bias Point analysis as well, but this should be very straightforward) and you will be given the appropriate starting point. While this circuit will be fairly simple, you can expect it to have a controlled current source that must be dealt with.
What are those principles?
If we have a transistor circuit that has a bandpass characteristic and is characterized by a single dominant pole at each end of the passband, then we can exploit our fundamental understanding of how capacitors behave as a function of frequency to significantly reduce the complexity of the required analysis - though it may still be very complex when all is said and done.
The basic, fundamental concept is that the impedance of a capacitor decreases with increasing frequency. At sufficiently low frequencies, it's influence on the overall circuit is fairly constant and similar to the influence that an open circuit would have. At sufficiently high frequencies, it's influence on the overall circuit is also fairly constant but is similar to the influence that a short circuit would have. At some point in between these two extremes is a frequency range for which neither assumption is reasonable and, in fact, the changing impedance of the capacitor within that frequency range has a significant impact on the behavior of the transfer function within that range.
Each capacitor in the circuit has an associated critical frequency at which it exercises this control over the transfer function. At frequencies significantly below that critical frequency it appears as an open circuit and at frequencies above that critical frequency it appears as a short circuit.
Because of the nature of the circuits we are restricting ourselves to, we can say the following things:
Typically, the three most important parameters we want to know concerning the transfer function for the circuit we are analyzing is the midband gain and the lower and upper cutoff frequencies of passband. If we can confidently identify which capacitors have critical frequencies below the passband and which have critical frequencies above the passband, then we can exploit the above conclusions to radically reduce the difficult of the following analysis. In most cases, external capacitors have critical frequencies below the passband while internal junction capacitances within the transistors tend to have critical frequencies above the passband. This is not always the case, but it is a reasonable starting point.
Hence, the midband gain can be determined by analyzing the circuit under the conditions that the low-frequency capacitors have been replaced by shorts and the high-frequency capacitors have been replaced by opens.
To find the lower cutoff frequency, we only need to determine the critical frequency of the capacitor that comes into play at the lower end of the passband - this capacitor is the dominant capacitor (at low frequencies) and the critical frequency of this capacitor serves as an estimate of the actual cutoff frequency. The circuit, at this point, is identical to the circuit used for the midband gain calculation with the exception that the dominant low-frequency capacitor is no longer a short-circuit but is acting as a real capacitor - the remainder continue to look like short circuits. The critical frequency is simply the reciprocal of the time constant formed by that capacitor and the resistance seen by that capacitor.
However, while we might know that certain capacitors are all low-frequency capacitors (and the rest are all high-frequency capacitors), we do not generally know which one is the dominant one. So we merely perform the above analysis for ALL of the low-frequency capacitors in turn and find out what each one's critical frequency would be IF that capacitor happened to be the dominant one. The true dominant one is then simply the capacitor with the highest critical frequency since all of the others have critical frequencies that are further away from the passband than the dominant capacitor's critical frequency. We could use this frequency as an estimate for the lower cutoff frequency but, it turns out, that a better estimate can usually be determined by using the information from all of the capacitors. In this case, we add up all of critical frequencies. Since the dominant capacitor has the highest critical frequency, the sum of the critical frequencies is going to be dominated by this capacitor - as it should be.
To find the upper cutoff frequency, we use the exact same concept. Recognizing that exactly one of the high-frequency capacitors is active at the upper cutoff frequency, we find the critical frequency for each one in turn, keeping the remainder of the high frequency capacitors appearing as opens. Again, we get the time constant for the critical frequency associated with each high-frequency capacitor. Since the dominant capacitor is going to be the one with the lowest critical frequency, we are looking for the one with the largest time constant. Upon identifying that capacitor, we could use the reciprocal of that time constant as our estimate of the upper cutoff frequency but, again, it turns out that we can get a better estimate by combining the information from all of the capacitors. Here, we add up all of the critical time constants. Analogous to the low-frequency case, since the dominant capacitor has the largest time constant, the sum of the critical time constants is going to be dominated by this capacitor - again, as it should be.
12 APR 03 - Power Transistors and heatsinks for DP#2 in the lab.
Since only one person has inquired about the power transistors for Design Project #2 and since time is getting pretty short, I've gone a head and put a small number of them in the lab - hopefully they won't walk away. There is a plastic tub on the desk where the UV erasers are located (near the windows) that contains some PNP and NPN transistors, some heat sinks (thermal resistance approximately 5C/W), some isolating spacers and some #6 screws and nuts. This may or may not be all you need for your output stage depending on how you build it.
18 MAR 03 - Syllabus changes due to blizzard
In order to balance the desire to not penalize people that couldn't make it in to class this week while still allowing us to have adequate time for Chapter 7, I have decided to basically swap the 1st week after Spring Break with the 2nd week after Spring Break. In addition, the due date for Design Project #2 is moved back one week. Notice that we will be starting Chapter 7 material in class immediately after Spring Break, spending two class periods on that, and then jumping back to Chapter 9 material for three classes to do the Review for exam, the Exam, and the Review of the exam. While I normally don't like to do that, it may actually work out well since it will give you a week to absorb some of the fundamental concepts before we actually start using them in earnest.
As for this week's quiz - it will be given the first day back from Spring Break. There will still be a quiz on the day we review for the exam - I think that was helpful as the mistakes that people made on the last Chapter Six quiz allowed me to give a head's up while handing out the exam and, for the most part, those same mistakes weren't repeated on the exam.
The first quiz for Chapter 7 will be given the Tuesday after the exam - the day that we review the exam. Normally there wouldn't be a quiz on that day but normally we wouldn't have covered a bunch of new material before the exam and I want to encourage people not to brush off that material.
18 MAR 03 - Help Session for 18 Mar 03 cancelled - school is closed.
I've just found out that the campus is now officially closed and that the building is locked. So we will not be able to have our help session this evening. If there is any interest, we can have it Thursday evening - weather permitting.
18 MAR 03 - Design Project #2 - partners allowed.
There was some confusion about this issue on the last design project which included a bad call on my part. Less than three days before the design project was due I received an e-mail from an unknown sender claiming to be from "The electronics class" that asked if it was okay to work in teams on the design project. The intent of the project was for everyone to work individually and my first inclination was to respond that it was way too late in the project to be asking for that kind of change. But I realized at that point that this had never been stated explicitly (at least in writing and I couldn't recall stating it verbally) and I was also aware that many people had, in fact, been working together on the project. So it became a matter of whether enforcing an unstated intention would result in people that had not understood that intention into a position where they wouldn't be able to turn what work that they had done. So, against my better judgment (and I stated this in my response to the e-mail) I said I would accept project reports from teams of people but pointed out that I had a real concern that the learning experience was unlikely to be evenly divided amongst the team members.
I have since had discussions with a couple of people that did understand that the project was intended to be a solo effort and who felt that they were therefore at a disadvantage compared to the teams. These people also remarked that, overall, they were glad that they did work along because they feel that they learned a tremendous amount as a result. This is a legitimate complaint and, other than explaining the situation and admitting that I had failed to make it clear what the expectation was at the beginning of the project and that I made a bad call at the end of the project, there was relatively little I could do to correct the situation other than keeping that in mind as I graded the reports.
I don't want that to happen with this design project and so I am making it clear that you may work in teams of no more than three people. As before, I feel that you will probably learn more if you work along but, I also realize that this isn't necessarily true for everyone. So that is a call that you need to make. However, I do need some sort of insight into the amount of effort contributed by each team member and so each person on the team will be expected to turn in (separate from the report) a sheet giving their assessment of the relative effort put forth by each member of the team - including themselves. See the update to the Design Project specs for details.
This will be a number from 0 to 100 that reflects your opinion of what fraction of the total work was done by each person. There are a couple of caveats here. First, the sum of everyone's score cannot exceed 100. Second, you can't simply assign each person equal credit and be done with it. In the tradition of companies such as Lincoln Electric, you may parcel out your 100 points pretty much as you see fit as long as no two peoples' scores are within 5 points of each other. This forces you to rank order people which is something that you will have to do at some point in your career.
18 MAR 03 - Quiz #7 delayed due to snow.
In addition to the snow that kept some students from making it to class, apparently there were also some access problems associated with the Quiz #7 Prep Sheet. It was uploaded over the weekend but the links to it appear not to have gotten updated. It works fine on my machine but, then again, my machine is the one the pages with the links were saved on and I have seen before that my browser can sometimes be stubborn about using it's locally cached pages even after I tell it to refresh and so that might have masked the problem.
I was willing to give the quiz anyway since the Prep Sheets are simply a bonus for your benefit, but I didn't want to penalize those that exercised good judgment in the face of the road conditions this morning and elected not to risk becoming weather statistics. So we will have the quiz on Thursday. If the weather system sticks around that long, then I will revisit it then.
FYI: Today we talked about power dissipation and thermal management of power BJTs. We had managed to get roughly a day ahead in the syllabus, so I focussed just on Sec 9.6 today and will focus on Sec 9.7 on Thursday.
07 MAR 03 - Don't forget everything you've learned!
Even though we are now working in a new chapter (Chapter Nine), that does not mean that you can forget everything that you've learned (or were supposed to learn) in Chapter Six. Aside from the point that doing so totally defeats the purpose of taking this course in the first place, concepts from Chapter Six (and all prior chapters plus all prior courses) form the foundation for the material in Chapter Nine. Furthermore, you most definitely want to be conversant will the material from Chapter Six plus especially the material in Chapter Four when we reach Chapter Seven in a few weeks.
If you do not have a good handle on the material in Chapter Six - and judging from the Exam #1 results this applies to a very large portion of the course - then it is up to you to overcome the identified deficiencies. As has been stated in class, you do NOT want to ignore this issue and assume that you will get through Chapter Seven unscathed. I am more than willing to overlook poor performance on Chapter Six if and only if your performance on Chapter Seven indicates that you have attained proficiency with the fundamental concepts that from Chapter Six.
My observations lead me to conclude that the deficiencies go to material that precedes this course including, for quite a few people, a general weakness in mathematics (particularly calculus) and basic circuit analysis. If you fall into this category, the you might consider sitting in on the appropriate courses as a refresher - many instructors will permit you to do this informally and, worst case, you may have to formally audit the course.
As for preparation for Chapter Seven specifically, you are once again strongly encouraged to work all of the problems from the Course Preview Assignment which most people unwisely chose to ignore. You should furthermore make sure that you completely understand all of the problems from Chapter Six.
We hit Chapter Seven on 10 Apr 03. That is right at five weeks from now and includes Spring Break. Make yourself a Study Plan and, if you get started right away and do not wait for the last minute, the additional burden should not be excessive. As a recommendation, I recommend that you do the following:
By "thoroughly study" it is meant that you actually work through the development of the equations along with the book - don't just read them, but actually make certain that you can DO them - that where they come from and what they mean make sense. You should find this much more tractable now that you have been through the material once and have a general perspective of how it all fits together.
Notice that if you maintain an average pace of only six pages and two problems per day that you can be finished with all of this prior to starting Chapter Seven in class.
As with all things, you can choose to ignore this recommendation. However, you do so at your own risk - do not expect the pace at which the Chapter Seven material is covered to slow as a result. The material in Chapter Seven is not trivial and you do not want to be struggling with basic concepts at the same time you are struggling with learning how to analyze the small-signal frequency response of multi-transistor circuits.
25 FEB 03 - Equipment and components for DP#1.
I got an e-mail from a student asking about this and figured that the answer would probably benefit more than just that one person.
Back at the beginning of the course (Day 2) I mentioned that I would have proto boards available for check out (that must be returned in order to get a grade in the course) and that you could use the components and test equipment in the Electronics Lab (Room 229). Campus Security was given a course roster with instructions that everyone on it had evening and weekend access to the lab - and keep in mind that the building is open 24 hours a day 7 days a week. If you get here and the lab is locked, just ask the security guard to unlock it or, if you can't find the guard, call Campus Security at x3111 (there is a phone on the wall near the vending machines in the lounge) and they will come over and open up the room.
Now, if you haven't had any lab courses (in that lab), you probably should swing by and talk to Ron (he can be found in Room 238) to see if there is anything you need to know or be checked out on and where to find things in the lab. One thing to keep in mind is that the tools and handheld meters are kept locked up when a lab isn't in session and so you will need to get Ron or an instructor with appropriate access to unlock them for you - or you can bring your own.
23 FEB 03 - Design Project #1 deadline approaching - don't let it sneak up on you!
Your Design Project #1 is DUE on 06 MAR 03. I am becoming concerned because no one has yet come to get their solderless breadboard that the department bought for everyone for your use on these design projects. Now, for some of you, you may have your own. Others may be diligently working away on your paper design and simulations and simply not be ready to start prototyping yet. That's fine if that's the case - though I strongly encourage you to build up your system one stage at a time and test it to be satisfied that the real world physical circuit does what you are expecting it to.
The project was assigned over a month ago. It is your responsibility to manage your time so as to complete the project on time - that was why I assigned it with so much lead time. If you choose to wait until the last minute and run out of time to do an adequate job, your grade will reflect it. There will be no deadline extensions and late submissions will not be accepted.
Be aware that the emphasis is more on being able to implement and test your design than on simulating it. So if you have to sacrifice one or the other, get the design built and tested!
If you find that you are having problems achieving the specified gain and linearity simultaneously, note that it is far easier to calibrate for non-spec gain than it is to correct for nonlinearity. So get the circuit to be linear at a lower gain and then characterize and document the non-spec gain performance.
Be careful not to fall into the mindset that you will simply be able to throw the components together and that it will work right away - unless you have very carefully considered all the aspects of your design, you are very likely to run into real-world performance limitations (that we have discussed in class and that have been dealt with as part of your homework assignments) that will force you to do major rework in order to achieve the specified outcome.
17 FEB 03 - No More Homework Collected
Honestly, for many students, I don't see that collecting and grading the homework is of any benefit. What I am seeing is work that is spiked from someone else with no apparent effort to understand what is being copied or work that is brute forced to come up with the answers that are in the back of the book regardless of how much magic or tortured math has to be invoked to make that happen. This is pointless. It's a waste of the student's time to turn in such a paper as they have learned nothing and, frankly, is a waste of my time (and somewhat of an insult) to grade as any feedback I offer is unlikely to actually advance that student's knowledge and understanding. This is not to say that I am seeing this in the majority of papers - I'm not. It is obvious that most people are making an honest effort and it is also obvious that some people are working together in a manner that is acceptable and productive. But I am seeing enough of the other behavior that collecting homework from everyone is pointless. The worst part is that the time I spend on papers that play these games is time that I could have spent providing more useful feedback to the students that are truly making an effort to work the homework based on their understanding of the material.
Definitely take the lessons learned on the first three homeworks to heart because the emphasis that I place on tracking units, showing your work, and avoiding magical methods will also be applied to the quizzes, projects, and exams.
Because of the added time that I am devoting to this class, between extended office hours and the newly added weekly help sessions, I simply don't have the time to spend four to eight hours grading each homework set, especially when a considerable portion of it falls into the above categories. Since I'm not convinced that collecting and grading the homework is actually being too beneficial for most students, no more will be collected. The homework portion of your grade will be based on the first three homeworks but the percentage of your total grade has been reduced from 25% to 10% which roughly corresponds to the fraction of the homework that has been collected and graded compared to what was originally intended. The exam weightings have been adjusted upward to compensate. I will furthermore replace your final homework grade with your final quiz grade if your quiz grade at the end of the semester is higher than your homework grade.
Homework will still be assigned, it just won't be collected. Does this mean that you can just ignore the assignment? Yes. It means precisely that. Is this advisable? No. You are highly unlikely to be prepared to take the quizzes or the exam without working the homework problems. Solutions to the homework problems will continue to be posted in the library but they will be posted at about the same time that the homework is assigned so that you can work the problem and then immediately check it against how I worked the problem.
I am hoping that this change in policy affords you the flexibility to tailor your study plan to suite your needs. If the material in this course is straightforward for you, then you can shift some focus to other courses since, clearly, it means that you can greatly reduce the amount of time you spend devoted to this class - but only YOU can determine if doing so is a wise decision for YOU.
For those that would like to continue getting feedback, you may turn in your homework and I should be able to pay quite a bit more attention to it. I ask that you not turn in problems that you are comfortable with - turn in only the problems that you are having difficulties with. Don't forget about my office hours (either the official ones or by appointment) and the Help Sessions - those are prime ways to get feedback as well. Whether you turn in anything or not will have no bearing on your grade per se, though I suspect that the people that take advantage of this opportunity will tend to be the ones that will do better in the course - at least better than they would have otherwise.
13 FEB 03 - Help Sessions Announced
Beginning next Tuesday (18 Feb 03) we will have weekly help sessions starting at 7pm and running until whenever we finish up (come and go as you please). I have reserved Room 239 (the one right next to the lounge) from 7pm to 9pm. I'm hoping that this fits with most peoples' schedule and if it turns out that it doesn't we can find another time. Most of the time we are together I would like to spend with you working on your homework problems or your design project or the review problems on the board and I'll be available to answer questions, offer hints, or point out things you are missing. I won't work the problem for you but I may work other, similar problems.
I'm willing to continue running these sessions, in addition to continuing to be available one-on-one, as long as there is interest and they appear to be productive.
11 FEB 03 - Homework #3 Example Problems posted in library
I have worked a few problems similar to some of the ones on your homework and have posted those solutions in the library reserve binder for this course. Hopefully seeing how I've approached these problems will help you as you work on yours. I will try to post a couple of problems for each future homework set but there are no promises.
10 FEB 03 - Homework #2 post-grading observations
While some people are still being sloppy with their units, there is a very noticeable improvement. Beginning now, the gloves come off and units errors get their full penalties - so if you are one of the people that still think you don't need to put in the effort to track your units, you will become one of the people that will be losing 20 to 40 points or more per homework set. The choice is entirely up to you.
It is still way too common to just throw an equation at the problem, frequently without any set-up work indicating where that relationship is coming from. This is not a good idea for a number of reasons. You will find that thoroughly setting up your problems will greatly reduce the number of blind alleys you proceed down and increase the chance that you will not overlook things. From a more practical standpoint, especially on the exams, it is impossible to assign partial credit if no work is shown. If you just plop an equation down and that equation is wrong I will have no idea where you came up with that equation and no idea whether it represents a minor typo or a major lack of comprehension. In this case you have made the grading pretty much an all-or-nothing situation.
You need to learn how to read keys from the problem statement. For instance, if no value of beta is given and nothing else in the problem indicates that you can't assume it to be infinity, then set it equal to infinity. On the other hand, if the question is asking how something is affected by beta, don't go setting beta equal to infinity in your computations - and saying that the collector current is about equal to the emitter current or that the base current is about zero is doing just that.
Also, if you are given that the large signal base-emitter voltage drop is 0.7V (and nothing more) then you may assume that it is acceptable to use 0.7V as the large signal base-emitter drop regardless of collector current. But if you are told that it is 0.7V at a specific collector current, then you have to ask why you are being given this added information - the correct conclusion is because it is NOT 0.7V at other collector currents and hence you are expected to adjust accordingly. Unless you are given other information (such as the voltage at another collector current or the temperature) then you can probably use the rule of thumb that the collector current changes by an order of magnitude for every 60mV change in the base-emitter voltage.
Many people are still confusing large signal and small signal concepts. Never lose sight of the fact that the total signal (be it a current, input signal, output signal, supply voltage, or whatever) is the superposition of the two.
Several people are either not doing the homework or are only doing a couple of problems. Clearly, doing and turning in a couple of problems is better than nothing. But the bigger problem is that if you don't do the homework, you are very unlikely to gain the skills and knowledge needed to either get good marks on the exam or, more importantly, use the information from this course in the "real world"
Remember the policy on Magical Methods - do not force your answer to be what you think it should be or what the back of the book says it should be. Your answer is what you get based on your work. I am very harsh on this - don't do it.
If I write, "Come see me," on your homework, I fully expect you to come see me. No one has yet to do so from the first assignment. If you think the problem will go away by ignoring it, you are wrong. Your homework grade will become a zero for that assignment and we will proceed from there. .
This homework set still took me about eight hours to go through, so expect for less detailed comments on the next one! Your base grade will be dictated by how correctly your basic approach is and this will be based upon a QUICK look at your work. If your work is hard to follow, I will NOT wade through it to see if you did it right. You would be well advised to make the effort to make your work very easy to follow.
06 FEB 03 - VT vs Vt
A student pointed out that my use of Vt for the thermal voltage was inconsistent with the book's use of VT. You've probably noticed that on many occasions I have written VT and then erased the subscript and rewrote it as Vt. I had thought that I was being consistent with the authors but the student was correct and I will try to change my ways. As the book pointed out back in Chapter 5 (see the footnote on p357) the proper symbol for both quantities is VT since both are large signal constant parameters. In order to avoid confusion between the two, the authors chose to arbitrarily violate the accepted convention (explained on p18) and use Vt for one of them. They decided to use VT for the thermal voltage and the altered one, Vt, for the threshold voltage - possibly because the chapter on FETs comes after the chapter on BJTs but more probably because they deal more with BJTs than with FETSs in the majority of the book..
In practice, VT is used for both quantities because there is little chance for confusion. If you are working with BJTs then it is only reasonable to interpret VT as the thermal voltage and if you are working with FETs it is only reasonable to interpret it as the threshold voltage. Even when you have BJTs and FETs in the same design it is not difficult to keep them straight because the manner in which they participate in the equations is so distinctive. But, at a time when you are first learning these things, the opportunity for confusion is much greater and so the authors chose to minimize the chance as much as possible.
I had decided to adopt the authors' notation and thought that I was doing that. But, apparently, I got it backwards. This probably stems from the fact that I interact with the threshold voltage much more frequently due to my profession as a CMOS IC designer and hence VT is engrained in my mind as the threshold voltage and when I see Vt I see something different and it is more natural for me to think of it as being the thermal voltage. To show how automatically you will learn to distinguish the two, once I got that mindset the fact that the authors were using VT for thermal voltage didn't draw my attention because the context of its use automatically and subconsciously established it as the thermal voltage.
I apologize for any confusion this has caused.
04 FEB 03 - Homework #1 post-grading observations
Your grade was composed of three components. The major one was the grade I would have assigned had the work you presented been complete and without penalties for failing to track units. The next component was a deduction for incomplete work at ten points per problem. The third was a penalty for failing to track units. Unless your failure to track units either caused an error or prevented you from catching an error, you only lost one point per problem no matter how many units errors you made. That will not continue. In the future, flagrant disregard for units will cost you about 20% to 30% of the problem value - and the occasional slip for someone that is otherwise diligent will be ignored or penalized very mildly.
But it is very apparent that many people did not believe me when I announced my policy on units the first week of class, they did not believe me when I outlined my policies regarding units and stressed the penalties on the Course Policies web page, and they did not believe me when I penalized them for units on the first quiz. So now those people have been penalized again on the homework - in several cases losing an additional 10% of their total score (one letter grade). The penalties for failing to track units will NOT go away - as pointed out above they will in fact get somewhat more severe. If you choose to ignore this policy and fail to track your units then you are choosing to lower your grade in the course by about two letter grades. Those are your options - make your choice and accept the consequences.
A few people had work that was very difficult to follow, but mostly it was readable. If I asked you where something came from, then that is an indication that either your work was too hard to follow or you need to provide more detail in your documentation. Most people could improve their presentation somewhat but, with those few exceptions, I don't have any major complaints on this score.
In response to the actions of just a couple of people, I have outlined my position on collaborative efforts on the Course Policies page.
I spent a total of seventeen hours grading this homework set - or about one hour per paper. I simply cannot afford to spend this much time on future sets. I hope that my comments on this first one are helpful in guiding your own self-study. From now on, I will be severely limiting myself to how long I spend on any one person's submission with the primarily goal being to assign a grade (using the system described for this first set as long as it proves workable). I may or may not be able to make more than a very few comments on just a few problems. You are now at the stage in your professional development where you should be taking responsibility for your own self-evaluation and corrections. The homework solutions will be posted in the library and it is your responsibility to compare your work to mine and determine if you worked the problem in a reasonable manner. Feel free to ask me questions about things you can't figure out after looking at my solution.
28 JAN 03 - Use of the Student Edition of PSpice
In anticipation of problems that people are going to have, it is in order to address this issue early on. Many students feel that the homework and, in particular, the design projects should be kept sufficiently limited in scope so that they can be simulated using the student edition of PSpice since that is free and you don't have to fight the limited number of seats for the full edition that are available on campus. While I certainly sympathize with this desire, it simply isn't practical in this particular course.
The Student Edition of PSpice is highly restricted - 10 transistors - to be of much use in a course that is completely centered around multi- transistor based circuits. A single stage amplifier with a differential pair, a cascode stage, a Wilson Mirror as an active load and a Wilson Mirror as the bias current source has ten transistors in it.
There is nothing I can do about these limitations and it is very difficult to devise meaningful design problems for a course such as this within those limitations - particularly for the material in Chapter 6.
To the degree that you can do your work using the Student Edition of PSpice - that's great. Keep in mind that not all students have access to a computer off campus - at least not one that they can load that software onto - and so you have an advantage if you can use it at all.
All students have access to the professional edition in the computer lab. Yes, there are not an unlimited number of seats. It's that way in the real world, too - trust me on this one! It is very, very seldom that all of the licenses are in use (outside of a class session that has specifically placed all of the students in the lab at the same time) and you have a good idea of when those times are going to be - namely just before a major assignment is due. With that knowledge, you have the option to choose to get your work done before the crunch time and avoid the conflicts. You also have the choice not to and I will be none too sympathetic about the complaints that arise as a result.
If you understand things like Thevenin Equivalent Circuits you can work with a stage at a time and develop an equivalent circuit for that stage and use that equivalent circuit in developing the other stages. That will go a long way toward letting you develop and evaluate your entire design within the component, node and transistor limitations of the Student Edition. Then you can go to the computer lab and simulate the actual entire circuit on the professional edition.
26 JAN 03 - Quiz Prep Sheets added
Quiz Prep sheets have been added to the sight - at least the first one. Go to the Syllabus and and click on a quiz in the "Due" column and you will be taken to the Prep Sheet for that quiz. These sheets work the same way that the Exam Review sheets do, namely that some or all of the questions will come off the prep sheet verbatim.
26 JAN 03 - Homework Hints
A hint for P4.29 has been posted to HW#1's webpage.
In general, whenever there are hints about homework problems they will be posted to that homework's webpage which can be accessed through the links on the syllabus. I will try to post a notice here, but may not always get that accomplished so try to get in the habit of checking the homework's page for the latest hints if you are having problems.
21 JAN 03 - Homework Due Date Change
A couple of students have inquired about the possibility of having homework due on Thursday so that questions that come up over the weekend can be discussed either in class or during my office hours on Tuesday. I don't have a problem with this, so the homework due dates have all been moved to Thursday.